1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a structure of contact between wiring layers in a semiconductor integrated circuit device manufactured at a high degree of integration and a method for forming the contact.
2. Description of the Related Art
A prior art structure of contact between wiring layers in a semiconductor integrated circuit device and a prior art method of forming the contact are described in, for example, IEDM 83, pp. 530-553 "A PLANAR METALLIZATION PROCESS--ITS APPLICATION TO TRI-LEVEL ALUMINUM INTERCONNECTION" Moriya et al., and Jpn. Pat. Appln. KOKOKU Publication No. 2-57707.
FIG. 1 is a pattern plan view showing a conventional contact portion of a semiconductor integrated circuit device, and FIG. 2 is a cross-sectional view taken along the line 2--2 of FIG. 1. As shown in FIGS. 1 and 2, an insulation film 101 such as a field oxide film is provided on a semiconductor substrate 100 constituted by silicon or the like. First-level wiring layers 102-1 and 102-2 are formed in the first direction on the insulation film 101. An insulation film 103 of BPSG or the like is provided on the insulation film 101 and wiring layers 102-1 and 102-2. A contact hole 104 is formed in the insulation film 103 located on the wiring layer 102-1 and filled with a conductive filler 105 such as tungsten. Second-level wiring layers 106-1 and 106-2 are provided on the insulation film 103 in the second direction perpendicular to the first direction. The first-level wiring layer 102-1 and the second-level wiring layer 106-1 are electrically connected to each other by the conductive filler 105. The regions around the contact portion of the wiring layers 102-1 and 106-1 are formed widely in order to prevent failed connections due to mask displacement at the time of forming the contact hole 104.
The foregoing contact portion is formed through the following steps. First an insulation film 101 is formed on a semiconductor substrate 100. If the insulation film 101 is a field oxide film, it is obtained by selectively oxidizing the major surface of the substrate 100 by, e.g., LOCOS. Secondly polysilicon or the like is deposited on the insulation film 101 to form first-level wiring layers 102-1 and 102-2 by patterning. An insulation film 103 is then formed on the resultant structure and its surface is planarized by reflow, CMP (Chemical Mechanical Polishing), or the like. After that, a contact hole 104 is formed in the insulation film 103 on the wiring layer 102-1 by anisotropic etching such as RIE. Tungsten, or the like is selectively grown on the wiring layer 102-1 in the contact hole 104 by LPCVD, or a conductive layer is formed on the entire surface of the insulation film 103 and etched back to leave it in the contact hole 104, with the result that the hole 104 is filled with a conductive filler 105. Finally tungsten, aluminum, or the like is deposited on the insulation film 103 by CVD, sputtering, etc. to form second-level wiring layers 106-1 and 106-2 by patterning.
However, according to the structure of the contact portion and the method of forming the same, as described above, the first-level and second-level wiring layers require a margin .DELTA..alpha. for mask alignment at each contact portion between the wiring layers. Assuming that the minimum dimension determined according to a design rule is D, the width of each wiring layer is D, the interval between the wiring layers is D+.DELTA..alpha., and the wiring pitch is 2D+.DELTA..alpha. which is an index of degree of integration. This margin .DELTA..alpha. is a hindrance to high degree of integration.